1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a capacitor having an electrode formed by electroplating, and a manufacturing method thereof.
2. Description of the Related Art
For the manufacture of a highly integrated dynamic random access memory (DRAM), methods have been suggested for thinning a dielectric film of a capacitor, to increase capacitance within a limited cell area, and for forming a lower electrode of the capacitor with a three-dimensional structure, to increase the effective area of the capacitor. Research has also actively pursued methods for replacing the dielectric film of the capacitor with a thin film having a high dielectric constant, for example, (Ba,Sr)TiO2 (abbreviated BST), PbZrTiO3 (abbreviated PZT) or (Pb,La)(Zr,Ti)O3 (abbreviated PLZT) films. Such dielectric films can be formed in a capacitor in the same way as a conventional dielectric film such as ONO or Ta2O5 film. First, a buried contact (BC) for the capacitor is formed using a conductive plug such as a doped polysilicon plug, and a lower electrode is formed thereon. The dielectric material is deposited on the lower electrode.
A capacitor using the high dielectric film typically employs an electrode material belonging to the platinum (Pt) group or their oxides, e.g., Pt, iridium (Ir), ruthenium (Ru), ruthenium oxide (RuO2) and iridium oxide (IrO2), as a material for electrodes. Platinum, while having an excellent resistance to oxidation, has a high reactivity with silicon. Thus, when elements of the Pt group or their oxides are used as electrode materials, unwanted diffusion and reactions are likely to occur between the electrode material and the doped polysilicon plug. Thus, a barrier layer capable of preventing the reaction and diffusion is necessary between the lower electrode and the conductive plug.
A conventional method of forming a lower electrode forms a conductive film of a metal belonging to the Pt group, and then dry-etches the conductive film to form the electrode. However, accurately dry-etching a film formed of metals belonging to the Pt group is particularly difficult when forming a memory device having an electrode with a width of less than 300 nm, e.g., in a DRAM with a capacity of 4 Gbit or more. Better methods for forming small electrodes are sought.
According to an embodiment of the present invention, an integrated circuit manufacturing process uses electroplating to form an electrode. The process includes forming a conductive film on a conductive plug connected to an active region of a semiconductor substrate, and on an interlayer dielectric (ILD) film surrounding the conductive plug. Then, a non-conductive pattern, which exposes a part of the conductive film that is on the conductive plug, is formed. Electroplating forms a metal film of the platinum (Pt) group on the exposed conductive film.
In an exemplary embodiment, the conductive film contains a material selected from a group consisting of Pt group metals, Pt group metal oxides, conductive perovskites, and mixtures thereof. The non-conductive pattern is boro-phospho-silicate glass (BPSG), spin-on glass (SOG), phospho-silicate glass (PSG), plasma enhanced SiH4 (PE-SiH4) oxide, plasma enhanced tetra-ethyl-ortho-silicate (PE-TEOS) oxide, high density plasma SiO2 (HDP-SiO2), high temperature oxide (HTO) film, SiOx, SiNx, SiONx, TiOx, AlOx, AlNx, or a mixture thereof. The lower electrode is Pt, Ir, Ru, Rh, Os, Pd, or a mixture thereof.
Manufacturing a capacitor further may include forming of a diffusion barrier film on the conductive plug and the ILD film before forming the conductive film. The conductive film would then be formed on the diffusion barrier film.
The lower electrode can have a rectangular cross-section, a T-shaped cross-section or a trapezoidal cross-section with a widest side on top. The cross-section of the lower electrodes depend on the shape of the side walls of openings in the non-conductive pattern and the time and rate of the electroplating.
The method according to the present invention may further include, after the forming of the lower electrode, removing of the non-conductive pattern and the conductive film to expose the ILD film. Then, a dielectric film is formed on the lower electrode, and an upper electrode formed on the dielectric film.
Preferably, the dielectric film is contains Ta2O5, SrTiO3 (STO), (Ba,Sr)TiO3 (BST), PbZrTiO3 (PZT), SrBi2Ta2O9 (SBT), (Pb,La)(Zr,Ti)O3, Bi4Ti3O12, or a mixture thereof. The upper electrode can be formed by chemical vapor deposition (CVD) or sputtering. Alternatively, the upper electrode may be formed by forming a seed layer on the dielectric film and then electroplating a Pt group metal film on the seed layer.
The method according to the present invention may further include forming a diffusion barrier layer film under the conductive film and removing the non-conductive pattern to the extent that the ILD film is exposed, after the forming of the lower electrode. At the same time, the conductive layer and the diffusion barrier film under the exposed conductive layer are removed. Spacers covering the side walls of the diffusion barrier film are formed on the exposed ILD film, and a dielectric film may be formed on the lower electrode and the ILD film. Then, an upper electrode may be formed on the dielectric film. Preferably, the spacers are SOG, HDP-SiO2, PE-SiH4, PE-TEOS, SiNx, SiONx, BPSG or PSG.
In accordance with another aspect of the present invention, a capacitor for a semiconductor memory device is formed using the above method. A lower electrode of the capacitor has a rectangular, T-shaped, trapezoidal or barrel-shaped cross-section. The electroplating makes it possible to form a lower electrode having various shapes.